The inventive concept relates to a delay-locked loop (DLL) circuit, and more particularly to a wideband DLL circuit that is used to synchronize not only phases of a high-frequency clock signal and an internal clock signal, but also phases of a low frequency clock signal and an internal clock signal.
DLL circuits are commonly used to synchronize clock signals applied to integrated circuit devices, such as memory devices and signal processing devices. In certain applications, a DLL circuit may be used to drop the frequency of a clock signal into a lower frequency band to reduce power consumption. Such specific applications notwithstanding, DLL circuits are generally used within dynamic random access memory (DRAM) while operating across a wide frequency range.
The operative frequency range of a DLL circuit (i.e., the range of frequencies across which the DLL circuit may successfully “lock” a target signal) is determined to a great extent by the sum of a “delay block” delay time and a “clock path” delay time. The delay block delay time is a variable delay defined by a conventionally understood delay block included in the DLL circuit. The clock path delay time is a delay defined by the load being driven by a clock signal generated by the DLL circuit.
A delay block within a DLL circuit generally includes a plurality of serially connected delay cells that function to delay an input clock signal for a predetermined delay time. In this regard, the respective delays provided by each of the plurality of series connected delay cells are typically the same length. Since each clock path delay time varies according to the type and/or the number of loads driven by a corresponding clock signal provided by the DLL circuit, it is necessary to carefully consider the clock path delay time whenever a DLL circuit is designed.
A DLL circuit typically generates “an internal clock signal” (i.e., a clock signal generated by the DLL circuit) by first applying a delay block delay time and a clock path delay time to “an external clock signal” (i.e., a clock signal provided from a source external to the DLL circuit), and then comparing the phase of the internal clock signal with the phase of the external clock signal. The DLL circuit may compare these two phases by varying the delay block delay time. When the phases of the internal clock signal and external clock signal are synchronized within a defined error range, the DLL circuit locks the delay block delay time and may then perform more finely tuned phase locking.
A “unit delay time” (i.e., the delay time provided by each of the plurality of series connected delay cells forming the delay block of a DLL circuit) will vary according to whether the DLL circuit is used to synchronize the phase of a relatively high frequency clock signal with the internal clock signal, or whether the DLL circuit is used to synchronize the phase of a relatively low frequency clock signal and the internal clock signal. (Hereafter, the terms “high frequency clock signal” and “low frequency clock signal” are used in a relative relationship. That is, the operating frequency of the high frequency clock signal is higher than the frequency of a low frequency clock signal). Thus, in order for a DLL circuit to accurately synchronize the phases of a high frequency clock signal and an internal clock signal, the unit delay time must be relatively small. Whereas, the DLL circuit may accurately synchronize the phases of the low frequency clock signal and internal clock signal using a relatively larger unit delay time.